SOI technology consists of separating a fine silicon layer (a few nanometres) on a silicon substrate by a relatively thick insulator layer (a few tens of nanometres as a general rule).
Integrated circuits produced in SOI technology exhibit a certain number of advantages. Such circuits generally exhibit lower electrical consumption for equivalent performance. Such circuits also induce lower parasitic capacitances, which make it possible to improve switching speed. Moreover, the phenomenon of parasitic triggering (known as “latchup”) encountered by metal-oxide-semiconductor (MOS) transistors in “bulk” technology can be avoided. Such circuits therefore turn out to be particularly suitable for applications of SoC (“Systems on Chip”) or MEMS (“Micro Electro-Mechanical Systems”) type. It is also noted that SOI integrated circuits are less sensitive to the effects of ionizing radiations and thus turn out to be more reliable in applications where such radiations may induce operating problems, in particular in space applications. SOI integrated circuits may in particular comprise random-access memories of SRAM (“Static Random Access Memory”) type or logic gates.
The reduction in the static consumption of logic gates while increasing their tripping speed forms the subject of much research. Certain integrated circuits in the course of development integrate logic gates with low consumption and also logic gates with high tripping speed. To generate these two types of logic gates on one and the same integrated circuit, the threshold voltage (abbreviated VT) of certain transistors is lowered to form logic gates with high tripping speed, and the threshold voltage of other transistors is increased to form logic gates with low consumption. In “bulk” technology, the modulation of the threshold voltage level of transistors of the same type is performed by differentiating their channel doping level. However, in fully depleted channel semi-conductor on insulator technology, better known by the acronym FDSOI (for “Fully Depleted Silicon On Insulator”), the doping of the channel is almost zero (1015 cm−3). Thus, the doping level of the channel of the transistors cannot therefore exhibit any significant variations, thereby preventing differentiation of the threshold voltages in this fashion.
In order to have distinct threshold voltages for various transistors in FDSOI technology, it is known to use an electrically biased ground plane (or “back-plane”) disposed between a thin isolating oxide layer and the silicon substrate. By altering the doping of the ground planes and their electrical bias, it is possible to improve the electrostatic control of these transistors, thereby making it possible to define various ranges of threshold voltages for these transistors. It is thus possible to have low-threshold-voltage transistors termed LVT (for “Low VT”, typically 400 mV), high-threshold-voltage transistors termed HVT (for “High VT”, typically 550 mV) and intermediate-threshold-voltage transistors termed RVT (for “Regular VT”, typically 450 mV).
In a known manner, such transistors exhibiting different threshold voltages can be integrated within one and the same integrated circuit. Such co-integration makes it possible in particular to benefit from several threshold voltage spans, together with better operating flexibility of the circuit.
FIGS. 1 and 2 illustrate an example of integrated circuit of a known type in 28 nm technology. FIGS. 1 and 2 are schematic sectional views of an integrated circuit at the level of nMos/pMos pairs respectively of RVT type and of LVT type. The integrated circuit comprises a bias circuit, for applying electrical biases Vdd and Gnd.
FIG. 1 represents a first cell of RVT type of the integrated circuit. The first cell comprises a semi-conducting substrate 44. This substrate 44 here exhibits a doping of type p, with a concentration of dopants of less than or equal to 1016 cm−3.
The first cell comprises:
a buried layer 43 of an electrically insulating material;
field-effect MOS transistors, namely an nMOS transistor ns and a pMOS transistor ps. The source, the drain and the channel of the transistor ns are formed in a semiconducting layer 11s disposed on the buried layer 43. The source, the drain and the channel of the transistor ps are formed in a semi-conducting layer 21s disposed on the buried layer 43;semi-conducting ground planes 41s and 42s are situated under the layer 43 and placed plumb, respectively, with the transistors ns and ps. The ground planes 41s and 42s respectively exhibit dopings of type p and n;semi-conducting wells extend depth-wise in continuity respectively with the ground planes 41s and 42s. The wells form a separation between the ground planes 41s and 42s and the substrate 44.
The ground plane 41s and the well disposed in continuity therewith are biased to Gnd by way of a P+ implanted zone 32s. The ground plane 42s and the well disposed in continuity therewith are biased to Vdd by way of an N+ implanted zone 33s. One and the same bias is applied to the gates of the transistors ns and ps.
The first cell is isolated at its periphery by isolation trenches 61 and 66. The implanted zones 31s and 32s are separated by an isolation trench 62. The implanted zone 32s is separated from the transistor ns by way of an isolation trench 63. The transistor ns is separated from the transistor ps by an isolation trench 64. The transistor ps is separated from the implanted zone 33s by way of an isolation trench 65.
FIG. 2 represents a second cell of LVT type of the integrated circuit. The second cell comprises:
a buried layer 43 of an electrically insulating material;
field-effect MOS transistors, namely an nMOS transistor nl and a pMOS transistor pl. The source, the drain and the channel of the transistor nl are formed in a semi-conducting layer 11l disposed on the buried layer 43. The source, the drain and the channel of the transistor pl are formed in a semi-conducting layer 21l disposed on the buried layer 43;semi-conducting ground planes 41l and 42l are situated under the layer 43 and placed plumb, respectively, with the transistors nl and pl. The ground planes 41l and 42l respectively exhibit dopings of type n and p;semi-conducting wells extend depth-wise in continuity respectively with the ground planes 41l and 42l. The wells form a separation between the ground planes 41l and 42l and the substrate 44.
The ground plane 41l and the well disposed in continuity therewith are biased to Gnd by way of an N+ implanted zone 32l. The ground plane 42l and the well disposed in continuity therewith are biased to Gnd by way of a P+ implanted zone 33l. One and the same bias is applied to the gates of the transistors nl and pl.
The second cell is isolated at its periphery by isolation trenches 61 and 66. The implanted zones 31l and 32l are separated by an isolation trench 62. The implanted zone 32l is separated from the transistor nl by way of an isolation trench 63. The transistor nl is separated from the transistor pl by an isolation trench 64. The transistor pl is separated from the implanted zone 33l by way of an isolation trench 65.
The transistors ns, ps, nl and pl are produced according to FDSOI technology. The transistor ns comprises a semi-conducting layer 11s, surmounted by a gate stack 12s. This layer 11s forms a channel 13s between a source and a drain of the transistor ns. The transistor nl comprises a semi-conducting layer 11l, surmounted by a gate stack 12l. This layer 11l forms a channel 13l between a source and a drain of the transistor nl. The transistor ps comprises a semi-conducting layer 21s, surmounted by a gate stack 22s. This layer 21s forms a channel 23s between a source and a drain of the transistor ps. The transistor pl comprises a semi-conducting layer 21l, surmounted by a gate stack 22l. This layer 21l forms a channel 23l between a source and a drain of the transistor pl. In a manner known in FDSOI technology, the channels 13s, 13l, 23s and 23l are in a depleted state and exhibit a very low doping level, of less than or equal to 1015 cm−3. The layer 43 exhibits a thickness of 25 nm, the layers 11s, 11l, 21s and 2l exhibit a thickness of 7 nm and the electrical thickness of the gate oxide in the gate stacks 12s, 12l, 22s and 22l is 1.5 nm. The gate stacks 12s and 12l comprise one and the same gate metal whose work function is 4.565 eV (middle of the forbidden band of the silicon, termed the midgap, of 4.6 eV−35 meV).
The gate stacks 22s and 22l comprise one and the same gate metal whose work function is 4.635 eV (midgap of 4.6 eV+35 meV).
The diagram of FIG. 3 illustrates the leakage currents and the conduction currents for the transistors ns, ps, nl and pl, when the first cell is optimized so that the transistors ns and ps exhibit one and the same threshold voltage level. It is then noted that, for the same doping levels of the wells and ground planes of the first and second cells, the discrepancy in threshold voltage between the transistors ns and nl is 70 mV whereas the discrepancy in threshold voltage between the transistors ps and pl is 140 mV. The optimization of the leakage current is therefore not the same for the transistors nl and pl and the threshold voltage levels for these transistors are not identical.
The diagram of FIG. 4 illustrates the leakage currents and the conduction currents for the transistors ns, ps, nl and pl, when the second cell is optimized so that the transistors nl and pl exhibit one and the same threshold voltage level. It is then noted that, for the same doping levels of the wells and ground planes of the first and second cells, the discrepancy in threshold voltage between the transistors ns and nl is 70 mV whereas the discrepancy in threshold voltage between the transistors ps and pl is 140 mV. The optimization of the leakage current is therefore not the same for the transistors ns and ps and the threshold voltage levels for these transistors are not identical.